[Prism54-devel] USB CVS snapshot
Feyd
feyd at seznam.cz
Wed Dec 15 15:01:02 UTC 2004
On Sat, 11 Dec 2004 00:17:33 +0100
Jean-Baptiste Note <jean-baptiste.note at wanadoo.fr> wrote:
>
> This is true unless the logic in the net2280 does very low-level work,
> for instance only translates operations on the PCI bus. Having a look at
> the exchanges on the 0x82 pipe, you'll see that the driver sends to the
> net2280 frames of zeros preceeded by addresses. PCI-wise this would corresponds
> to a DMA buffer, i'm sure. (they were values i didn't know how to interpret
> before running ndiswrapper in full debug mode and seeing that they realy
> were urbs addresses)
The field is supposed to be the request id I guess, the 32bit windows driver
stores the buffer address there.
>
> In this case, the net2280 could implement only the logic to map DMA
> transferts to USB transfers, and not interract at all with the firmware
> ; in the same way i guess the net2280 vendor could sell glue code
> translating a windows PCI driver to a USB driver with practically no change.
That makes sense. But what I find in the logs still seems prism specific, the
NET2280 is given too few information by the driver and knows too much what to
do :) It is not completely clear to me what happens there, maybe someone will
have a clue, or correct me if I overlooked something:
The read on the 0x82 is allways triggered by writing '6c 0[678] 02 00' to
the 0x0[12]. At the start 0x02 is used and the EEPROM read, later 0x01 is
used, for the card management I think. The write to the 0x02 is split to
two parts and the size is followed by '02 00', the write to the 0x01 is
solid and there is '00 00' after the size. Before the write to the 0x01
ISL38XX_DEV_INT_DATA is triggered, between the two writes to the 0x02
ISL38XX_DEV_INT_MGMT is triggered. A while after the write, data on 0x82
is read (becouse of irq triggered by the chip I think). Data packets are
sent on 0x01 using '00 02 02 00' as the selector, and received on 0x81,
again by irq I suppose.
Maybe the old firmware could work if it shares the queue management API
with the new. If it was the case, I would expect the SoftMAC cards respond
with an error instead of timeout, but this could be caused by another issue,
so yes, maybe the old firmware will work :)
the EEPROM read:
--- TRANSFER REQUEST ---
[OUT >934 <935 +1 ] 02 -> 00000000: [6c 06 02 00] [0c 04] [02 00] 00 00 00 00 00 00 00 00
[6c 06 02 00] target selector?
[0c 04] size
[02 00] fragments?
------
--- IRQ TRIGGER ---
[OUT >935 <935 +0 ] 0e -> 00000000: [0f 08] [00 00 00 40] [80 00 00 00]
[0f 08] target selector
[00 00 00 40] ISL38XX_DEV_INT_REG
[80 00 00 00] ISL38XX_DEV_INT_MGMT
------
--- DATA WRITEN ---
[OUT >935 <935 +0 ] 02 -> 00000000: [00 80 00 04] [b0 76 33 81] [0c 00 00 00] [00 00] [fc 03]
-> 00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-> 00000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[snip]
[00 80 00 04] magic1
[b0 76 33 81] request id
[0c 00 00 00] magic2
[00 00] offset
[fc 03] size
------
--- DATA READ ---
[IN >852 <1029 +177 ] 82 <- 00000000: 0c 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00
<- 00000010: 00 80 00 04 b0 76 33 81 0c 00 00 00 00 00 fc 03
<- 00000020: 47 4d 55 aa 00 00 00 00 ff ff ff ff 09 00 01 00
<- 00000030: 58 58 58 58 58 58 00 00 00 00 00 00 00 00 00 00
<- 00000040: 07 00 03 00 30 30 30 63 34 31 64 61 32 39 34 63
<- 00000050: 04 00 01 01 00 0c 41 da 29 4c 0b 00 01 10 00 00
<- 00000060: 0f 00 8b 00 01 00 ff 00 00 00 09 00 03 00 01 00
<- 00000070: 1f 00 03 00 02 10 03 86 01 55 05 00 05 19 ff 7f
<- 00000080: ff 7f 82 00 67 fe 3a 00 03 19 00 0e 6c 09 3b 39
<- 00000090: 2e 2d 80 47 71 09 3b 38 2e 2d 80 47 76 09 3b 38
<- 000000a0: 2e 2c 80 47 7b 09 3b 37 2f 2c 80 47 80 09 3c 37
<- 000000b0: 2f 2b 80 47 85 09 3c 36 2f 2b 80 48 8a 09 3c 36
<- 000000c0: 2f 2a 80 48 8f 09 3c 36 2f 2b 80 48 94 09 3d 37
<- 000000d0: 2f 2b 80 48 99 09 3d 37 2f 2b 80 48 9e 09 3d 37
<- 000000e0: 2f 2c 80 48 a3 09 3e 38 2f 2c 80 47 a8 09 3e 38
<- 000000f0: 2f 2c 80 47 b4 09 3e 38 2f 2c 80 47 b9 00 04 19
<- 00000100: 00 0e 08 80 6c 09 53 77 be 4b 37 9b 43 09 7e 37
<- 00000110: da 5a 2b bd 3d 1f ab 23 13 a0 0c 00 96 00 71 09
<- 00000120: 53 77 b9 4b 37 97 43 09 7b 37 da 58 2b bd 3b 1f
<- 00000130: ab 22 13 a0 0a 00 96 00 76 09 53 76 b5 4b 38 93
<- 00000140: 43 0a 78 37 db 56 2b be 39 1f ac 20 13 a0 09 00
<- 00000150: 96 00 7b 09 53 75 b1 4b 37 90 43 0a 75 37 dc 54
<- 00000160: 2b bf 37 1f ac 1e 13 a1 07 00 97 00 80 09 53 74
<- 00000170: ad 4b 37 8d 43 0b 72 37 dc 52 2b bf 36 1f ad 1d
<- 00000180: 13 a1 06 00 97 00 85 09 53 72 a9 4b 37 8a 43 0b
<- 00000190: 70 37 dd 50 2b c0 34 1f ad 1b 13 a2 04 00 97 00
<- 000001a0: 8a 09 54 79 a9 4c 3c 8a 44 0f 70 38 e0 50 2c c2
<- 000001b0: 35 20 af 1c 14 a3 05 00 97 00 8f 09 53 76 a7 4b
<- 000001c0: 39 88 43 0c 6e 37 de 4e 2b c1 33 1f ae 1a 13 a2
<- 000001d0: 03 00 97 00 94 09 53 7a a9 4b 3c 8a 43 0e 6f 37
<- 000001e0: de 4f 2b c1 33 1f ae 1b 13 a2 04 00 98 00 99 09
<- 000001f0: 52 76 a7 4a 37 88 42 0a 6e 36 dc 4d 2a bf 32 1e
<- 00000200: ad 19 12 a1 02 00 98 00 9e 09 52 79 a9 4a 39 89
<- 00000210: 42 0b 6f 36 dc 4e 2a be 32 1e ac 1a 12 a1 03 00
<- 00000220: 98 00 a3 09 51 73 a7 49 34 87 41 06 6d 35 d9 4c
<- 00000230: 29 bc 31 1d ab 18 11 a0 01 00 98 00 a8 09 51 76
<- 00000240: aa 49 35 89 41 07 6e 35 d8 4d 29 bc 31 1d ab 18
<- 00000250: 11 a0 01 00 98 00 b4 09 51 76 aa 49 35 89 41 07
<- 00000260: 6e 35 d8 4d 29 bc 31 1d ab 18 11 a0 01 00 98 00
<- 00000270: 47 00 06 19 6c 09 03 00 ff 03 f8 03 00 01 71 09
<- 00000280: 03 00 ff 03 f7 03 01 01 76 09 04 00 ff 03 f7 03
<- 00000290: fd 00 7b 09 03 00 ff 03 f8 03 fd 00 80 09 03 00
<- 000002a0: ff 03 f8 03 01 01 85 09 03 00 ff 03 f8 03 01 01
<- 000002b0: 8a 09 04 00 ff 03 f8 03 ff 00 8f 09 03 00 ff 03
<- 000002c0: f8 03 00 01 94 09 03 00 ff 03 f8 03 02 01 99 09
<- 000002d0: 03 00 ff 03 f8 03 02 01 9e 09 04 00 ff 03 f8 03
<- 000002e0: ff 00 a3 09 03 00 ff 03 f8 03 fe 00 a8 09 03 00
<- 000002f0: ff 03 f8 03 01 01 b4 09 03 00 ff 03 f9 03 fd 00
<- 00000300: 07 00 07 10 10 00 00 00 30 00 00 00 40 00 00 00
<- 00000310: 03 00 08 10 30 00 00 00 03 00 00 11 08 08 08 08
<- 00000320: 02 00 00 00 f9 f5 02 00 00 00 ff ff ff ff ff ff
<- 00000330: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 00000340: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 00000350: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 00000360: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 00000370: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 00000380: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 00000390: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 000003a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 000003b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 000003c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 000003d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 000003e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 000003f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 00000400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<- 00000410: ff ff ff ff ff ff ff ff ff ff ff ff
------
card management:
--- IRQ TRIGGER ---
[OUT >2698 <2699 +1 ] 0e -> 00000000: [0f 08] [00 00 00 40] [40 00 00 00]
[0f 08] target selector
[00 00 00 40] ISL38XX_DEV_INT_REG
[40 00 00 00] ISL38XX_DEV_INT_DATA
------
--- TRANSFER REQUEST + DATA WRITEN ---
[OUT >2698 <2699 +1 ] 01 -> 00000000: [6c 06 02 00] [30 00] [00 00] 00 00 00 00 00 00 00 00
-> 00000010: [00 80 24 00] [50 05 3a 81] [0a 00 00 00] 00 00 00 00
-> 00000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-> 00000030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[6c 06 02 00] selector
[30 00] size
[00 00] fragments?
[00 80 24 00] magic1
[50 05 3a 81] req. id
[0a 00 00 00] magic2
------
--- DATA READ ---
[IN >1698 <2699 +1001 ] 82 <- 00000000: 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
<- 00000010: 00 80 24 00 50 05 3a 81 0a 00 00 00 03 00 00 00
<- 00000020: 00 00 00 00 00 00 00 00 47 00 00 00 00 00 00 00
<- 00000030: 00 00 00 00 0e 15 1b 00 00 00 00 00 18 00 00 00
------
packet transmit:
--- IRQ TRIGGER ---
[OUT >1700 <1700 +0 ] 0e -> 00000000: 0f 08 00 00 00 40 40 00 00 00
[0f 08] target selector
[00 00 00 40] ISL38XX_DEV_INT_REG
[40 00 00 00] ISL38XX_DEV_INT_DATA
------
--- DATA WRITEN ---
[OUT >1700 <1700 +0 ] 01 -> 00000000: [00 02 02 00] [34 00] [00 00] 00 00 00 00 00 00 00 00
-> 00000010: 01 80 28 00 00 00 00 00 00 00 00 00 00 00 00 0c
-> 00000020: 41 da 29 4c ff ff ff ff ff ff 00 ba 01 00 00 00
-> 00000030: 00 00 00 00 00 00 00 00 0c 48 02 00 10 06 03 00
-> 00000040: 00 00 42 ed
[00 02 02 00] selector
[34 00] size
[00 00] fragments?
------
packet receive:
--- DATA READ ---
[IN >1787 <1889 +102 ] 81 <- 00000000: [69 00] 00 00 00 00 00 00 00 00 00 00 00 00 00 00
<- 00000010: 4d 00 55 00 76 09 00 00 46 00 00 c5 9f ba 0e 00
<- 00000020: 00 00 00 00 80 00 00 00 ff ff ff ff ff ff 00 04
<- 00000030: e2 80 9c 8e 00 04 e2 80 9c 8e 20 52 f6 e1 7d c8
<- 00000040: 3d 00 00 00 64 00 21 00 00 0f 43 5a 46 72 65 65
<- 00000050: 2e 4e 65 74 2e 46 65 79 64 01 04 82 84 8b 96 03
<- 00000060: 01 01 2a 01 03 32 08 0c 12 18 24 30 48 60 6c 05
<- 00000070: 04 00 01 00 00 52 2b 4e 30 eb 59 1a
[69 00] size
------
Feyd
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