[Prism54-devel] [Bug 67] hard hang on readl

[bugzilla-daemon@mcgrof.com]

http://prism54.org/cgi-bin/bugzilla/show_bug.cgi?id=67





------- Additional Comments From vda@port.imtp.ilyichevsk.odessa.ua  2004-03-12 13:16 -------
> May be we can resort to a PCI quirk that will fix that.

That was (is?) my hope too. I tried to reprogram southbridge
but nothing short of setting mdma0 on IDE helped.

Maybe it is possible to reprogram prism54 card instead, but
so far I have no doc for it and only this in driver code:

prism54_probe(struct pci_dev *pdev, const struct pci_device_id *id) {
...
/* check whether the latency timer is set correctly */
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency_tmr);
if (latency_tmr < PCIDEVICE_LATENCY_TIMER_MIN) {
    /* set the latency timer */
    pci_write_config_byte(pdev, PCI_LATENCY_TIMER,
                                     PCIDEVICE_LATENCY_TIMER_VAL);
}
...
/* 0x40 is the programmable timer to configure the response timeout (TRDY_TIMEOUT)
* 0x41 is the programmable timer to configure the retry timeout (RETRY_TIMEOUT)
* The RETRY_TIMEOUT is used to set the number of retries that the core, as a
* Master, will perform before abandoning a cycle. The default value for
* RETRY_TIMEOUT is 0x80, which far exceeds the PCI 2.1 requirement for new
* devices. A write of zero to the RETRY_TIMEOUT register disables this
* function to allow use with any non-compliant legacy devices that may
* execute more retries.
*
* Writing zero to both these two registers will disable both timeouts and
* *can* solve problems caused by devices that are slow to respond.
*/
       pci_write_config_byte(pdev, 0x40, 0);
       pci_write_config_byte(pdev, 0x41, 0);

Fiddling with these _may_ help



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