[Prism54-devel] USB devel Fw: Email seems to work again ;-)
Feyd
feyd@seznam.cz
Tue, 6 Apr 2004 16:11:21 +0200
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Begin forwarded message:
Date: Sat, 27 Mar 2004 16:54:28 +0100
From: Feyd <feyd@seznam.cz>
To: Johannes Steingraeber <Jo_Stein@web.de>
Cc: Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>,
<prism54-devel@prism54.org>
Subject: Re: Email seems to work again ;-)
On Sat, 27 Mar 2004 14:56:54 +0100
Feyd <feyd@seznam.cz> wrote:
>
> 0x0d write reg
> 0x0e write reg
> 0x8d read reg
> 0x8e read reg
After looking on the output with timestamps, I think I understand it a bit
more:
0x0d/0x8d: accesses the usb<->pci bridge (may be)
0x0e/0x8e: accesses the prism chip
marian@alfa:~/perl$ grep "0d ->" filtered.log | cut -b-21 | sort -u
0d -> 00000000: 03 00
0d -> 00000000: 0f 00
0d -> 00000000: 1f 00
marian@alfa:~/perl$ grep "0e ->" filtered.log | cut -b-21 | sort -u
0e -> 00000000: 0f 08
0e -> 00000000: 83 08
0e -> 00000000: 8f 08
the 0x0e uses three "ports", [0f 08] to access the devices mmio,
[83 08] and [8f 08] to access probably the devices pci configuration space
the 80/00 seems to select the space, the 03/0f the operand size
similar applies to the 0x0d pipe, and they allways differ in the second
byte, so maybe the selection of device is done by that and not by the
used endpoint
Feyd
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[OUT >660 <660 +0 ] 0d -> 00000000: 1f 00 50 00 00 00 # read a statusreg
[IN >660 <660 +0 ] 8d <- 00000000: 3e 00 00 00
[OUT >660 <660 +0 ] 0d -> 00000000: 1f 00 50 00 00 00 3e 00 00 00 # stop
[OUT >760 <761 +1 ] 0d -> 00000000: 1f 00 50 00 00 00 3d 00 00 00 # start
[OUT >861 <861 +0 ] 0d -> 00000000: 1f 00 00 00 00 00 24 02 00 00 # initialize something after 100ms
[OUT >881 <881 +0 ] 0d -> 00000000: 03 00 04 00 00 00 06 00 00 00 # enable mmio and busmaster (16 bit)
[OUT >881 <881 +0 ] 0d -> 00000000: 0f 00 10 00 00 00 00 00 00 10 # set base address
[OUT >881 <881 +0 ] 0d -> 00000000: 03 00 06 00 00 00 # read status reg (16 bit)
[IN >881 <881 +0 ] 8d <- 00000000: 06 00 00 02
[OUT >881 <882 +1 ] 0d -> 00000000: 03 00 06 00 00 00 06 20 00 00 # wite back (status | PCI_STATUS_REC_MASTER_ABORT) (why?)
[OUT >882 <882 +0 ] 0d -> 00000000: 1f 00 88 00 00 00 # read revision?
[IN >882 <882 +0 ] 8d <- 00000000: 02 02 00 00
[OUT >882 <882 +0 ] 0d -> 00000000: 1f 00 24 03 00 00 04 00 00 00
[OUT >882 <882 +0 ] 0d -> 00000000: 1f 00 64 03 00 00 04 00 00 00
[OUT >882 <882 +0 ] 0d -> 00000000: 0f 00 18 00 00 00 00 00 00 20 # set base address_2
[OUT >882 <883 +1 ] 0e -> 00000000: 83 08 04 00 01 00 06 00 00 00 # set busmater, mmio
[OUT >883 <883 +0 ] 0e -> 00000000: 83 08 40 00 01 00 00 00 00 00 # pci_write_config_byte(pdev, 0x40, 0)
[OUT >883 <883 +0 ] 0e -> 00000000: 8f 08 10 00 01 00 00 00 00 40 # set base address?
[OUT >883 <883 +0 ] 0d -> 00000000: 1f 00 24 00 00 00 00 00 00 00
[OUT >883 <883 +0 ] 0d -> 00000000: 1f 00 2c 00 00 00 00 00 00 01
[OUT >883 <884 +1 ] 0e -> 00000000: 0f 08 00 00 00 40 08 00 00 00 # writel(ISL38XX_DEV_INT_REG, ISL38XX_DEV_INT_WAKEUP)
[OUT >903 <903 +0 ] 0e -> 00000000: 0f 08 00 00 00 40 20 00 00 00 # writel(ISL38XX_DEV_INT_REG, 0x20)
[OUT >923 <923 +0 ] 0e -> 00000000: 0f 08 78 00 00 40 # r = readl(ISL38XX_CTRL_STAT_REG)
[IN >923 <923 +0 ] 8e <- 00000000: db 48 80 00
[OUT >923 <923 +0 ] 0e -> 00000000: 0f 08 78 00 00 40 db 48 00 00 # writel(ISL38XX_CTRL_STAT_REG, r & ~(RESET | RAMBOOT | CLKRUN))
[OUT >923 <924 +1 ] 0e -> 00000000: 0f 08 78 00 00 40 db 48 00 10 # writel(ISL38XX_CTRL_STAT_REG, r & ~(RAMBOOT | CLKRUN) | RESET)
[OUT >924 <924 +0 ] 0e -> 00000000: 0f 08 78 00 00 40 db 48 00 00 # writel(ISL38XX_CTRL_STAT_REG, r & ~(RESET | RAMBOOT | CLKRUN))
[OUT >1024 <1024 +0 ] 0e -> 00000000: 0f 08 18 00 00 40 00 00 00 00 # writel(ISL38XX_INT_EN_REG, 0)
[OUT >1024 <1025 +1 ] 0e -> 00000000: 0f 08 10 00 00 40 # r = readl(ISL38XX_INT_IDENT_REG)
[IN >1025 <1025 +0 ] 8e <- 00000000: 00 40 00 00
[OUT >1025 <1025 +0 ] 0e -> 00000000: 0f 08 14 00 00 40 00 40 00 00 # writel(ISL38XX_INT_ACK_REG, r)
[OUT >1025 <1025 +0 ] 0d -> 00000000: 1f 00 2c 03 00 00 00 02 00 00
[OUT >1025 <1025 +0 ] 0d -> 00000000: 1f 00 4c 03 00 00 00 02 00 00
[OUT >1025 <1025 +0 ] 0d -> 00000000: 1f 00 6c 03 00 00 00 02 00 00
[OUT >1025 <1026 +1 ] 0d -> 00000000: 1f 00 8c 03 00 00 00 02 00 00
[OUT >1026 <1026 +0 ] 0d -> 00000000: 1f 00 2c 03 00 00 00 02 00 00
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