[Prism54-devel] USB devel Fw: Email seems to work again ;-)
Feyd
feyd@seznam.cz
Tue, 6 Apr 2004 16:09:28 +0200
Hi,
forwarding what we found with Johannes.
Feyd
Begin forwarded message:
Date: Sat, 27 Mar 2004 14:56:54 +0100
From: Feyd <feyd@seznam.cz>
To: Johannes Steingraeber <Jo_Stein@web.de>
Cc: prism54-devel@prism54.org
Subject: Re: Email seems to work again ;-)
Hi,
Im trying to understand what the endpoints are for and how to work with them.
Thats what I think I understand:
0x01 tx data
0x02 tx mgmt
0x81 rx data
0x82 rx mgmt
first 16 bytes of received data is header begining with the length of the data,
the actualy received data are padded to be multiple of 4 bytes
beacon received from ap I think
81 <- 00000000: 69 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
<- 00000010: 4d 00 55 00 76 09 00 00 65 00 00 c5 02 a8 0d 00
<- 00000020: 00 00 00 00 80 00 00 00 ff ff ff ff ff ff 00 04
<- 00000030: e2 80 9c 8e 00 04 e2 80 9c 8e 20 0d ec a1 cf 9e
<- 00000040: 0a 00 00 00 64 00 21 00 00 0f 43 5a 46 72 65 65
<- 00000050: 2e 4e 65 74 2e 46 65 79 64 01 04 82 84 8b 96 03
<- 00000060: 01 01 2a 01 07 32 08 0c 12 18 24 30 48 60 6c 05
<- 00000070: 04 00 01 00 00 6d 3a f0 97 eb 59 1a
transmited packet, the ethernet packet begins at 0x50, I dont know it the data
from 0 to 0x4f are usb adaptor or wireless specific
01 -> 00000000: 6c 06 02 00 79 00 00 00 00 00 00 00 00 00 00 00
-> 00000010: 00 40 3d 00 48 07 c8 fe 01 00 07 07 00 00 00 00
-> 00000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-> 00000030: 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00
-> 00000040: 00 00 02 7f 23 00 00 00 04 00 00 00 00 00 00 00
-> 00000050: 00 04 e2 80 9c 8e 00 0c 41 da 29 4c 00 04 e2 80
-> 00000060: 9c 8e 00 00 21 05 01 00 00 0f 43 5a 46 72 65 65
-> 00000070: 2e 4e 65 74 2e 46 65 79 64 01 04 02 04 0b 16 32
-> 00000080: 08 0c 12 18 24 30 48 60 6c 00 00 00
0x0d write reg
0x0e write reg
0x8d read reg
0x8e read reg
write:
magic register value maybe value of next register etc
[ xx xx ] [ xx xx xx xx ] [ xx xx xx xx ] ....
read:
magic register
[ xx xx ] [ xx xx xx xx ]
value
[ xx xx xx xx ]
Comments contain your observations and my gueses:
0d -> 00000000: 1f 00 50 00 00 00
8d <- 00000000: 3e 00 00 00
0d -> 00000000: 1f 00 50 00 00 00 3e 00 00 00
0d -> 00000000: 1f 00 50 00 00 00 3d 00 00 00
0d -> 00000000: 1f 00 00 00 00 00 24 02 00 00
0d -> 00000000: 03 00 04 00 00 00 06 00 00 00
0d -> 00000000: 0f 00 10 00 00 00 00 00 00 10
0d -> 00000000: 03 00 06 00 00 00
8d <- 00000000: 06 00 00 02
0d -> 00000000: 03 00 06 00 00 00 06 20 00 00
0d -> 00000000: 1f 00 88 00 00 00 # read revision? mine says 02 02 00 00
8d <- 00000000: 03 02 00 00
0d -> 00000000: 1f 00 24 03 00 00 04 00 00 00
0d -> 00000000: 1f 00 64 03 00 00 04 00 00 00
0d -> 00000000: 0f 00 18 00 00 00 00 00 00 20
0e -> 00000000: 83 08 04 00 01 00 06 00 00 00 # set busmater, mmio?
0e -> 00000000: 83 08 40 00 01 00 00 00 00 00 # pci_write_config_byte(pdev, 0x40, 0)?
0e -> 00000000: 8f 08 10 00 01 00 00 00 00 40 # set base address?
0d -> 00000000: 1f 00 24 00 00 00 00 00 00 00
0d -> 00000000: 1f 00 2c 00 00 00 00 00 00 01
0e -> 00000000: 0f 08 00 00 00 40 08 00 00 00 # writel(ISL38XX_DEV_INT_REG, ISL38XX_DEV_INT_WAKEUP)
0e -> 00000000: 0f 08 00 00 00 40 20 00 00 00 # writel(ISL38XX_DEV_INT_REG, 0x20)
0e -> 00000000: 0f 08 78 00 00 40 # r = readl(ISL38XX_CTRL_STAT_REG)
8e <- 00000000: db 48 80 00
0e -> 00000000: 0f 08 78 00 00 40 db 48 00 00 # writel(ISL38XX_CTRL_STAT_REG, r & ~(RESET | RAMBOOT | CLKRUN))
0e -> 00000000: 0f 08 78 00 00 40 db 48 00 10 # writel(ISL38XX_CTRL_STAT_REG, r & ~(RAMBOOT | CLKRUN) | RESET)
0e -> 00000000: 0f 08 78 00 00 40 db 48 00 00 # writel(ISL38XX_CTRL_STAT_REG, r & ~(RESET | RAMBOOT | CLKRUN))
0e -> 00000000: 0f 08 18 00 00 40 00 00 00 00 # writel(ISL38XX_INT_EN_REG, 0)
0e -> 00000000: 0f 08 10 00 00 40 # r = readl(ISL38XX_INT_IDENT_REG)
8e <- 00000000: 00 40 00 00
0e -> 00000000: 0f 08 14 00 00 40 00 40 00 00 # writel(ISL38XX_INT_ACK_REG, r)
0d -> 00000000: 1f 00 2c 03 00 00 00 02 00 00
0d -> 00000000: 1f 00 4c 03 00 00 00 02 00 00
0d -> 00000000: 1f 00 6c 03 00 00 00 02 00 00
0d -> 00000000: 1f 00 8c 03 00 00 00 02 00 00
0d -> 00000000: 1f 00 2c 03 00 00 00 02 00 00
Feyd