[Prism54-devel] Question on prism54 driver

[Jean-Baptiste Note]

Dear list,

Going through the prism54 code for reuse in the softmac driver, i
stumbled accross inconsistencies in the queue management functions for
the mgmt rx queue and the data rx queue that i cannot understand.

Is there any reason that we have the following call in
islpci_mgt_receive (file islpci_mgt.c):

		/* Ensure the results of device DMA are visible to the CPU. */
		pci_dma_sync_single(priv->pdev, buf->pci_addr,
				    frag_len, PCI_DMA_FROMDEVICE);

but have nothing of the sort in islpci_eth_receive (file islpci_eth.c) ?

In the same spirit, the control block is also written by DMA by the
device, I guess ; so how comes we don't have such a syncing call in the
interrupt handler before accessing the control block's values (file
islpci_dev.c) ?

Am i missing something very obvious or very subtle ? -- should shared
memory be always sync'd before reading, or should we avoid it in cases
where we know it's not necessary, as an optimization ?

JB

-- 
Jean-Baptiste Note
+33 (0)6 83 03 42 38
jean-baptiste.note at wanadoo.fr