[Prism54-devel] [Bug 67] hard hang on readl

[bugzilla-daemon@mcgrof.com]

http://prism54.org/cgi-bin/bugzilla/show_bug.cgi?id=67





------- Additional Comments From vda@port.imtp.ilyichevsk.odessa.ua  2004-03-10 19:01 -------
I slowed down IDE to mdma0, now UDP flood + heavy IDE write does not
kill the box. I even added 100Mbit ethernet flood (unidirectional)
to the mix. PCI bus still does not die.

mdma1 and udma0 result in _extreme_ PCI bus congestion and eventually
crash kernel in my _wired_ ethernet driver ;)

Will run stress test with mdma0 overnight.

By the way, what's this:

int
prism54_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
...
        /* 0x40 is the programmable timer to configure the response timeout
(TRDY_TIMEOUT)
         * 0x41 is the programmable timer to configure the retry timeout
(RETRY_TIMEOUT)
         *      The RETRY_TIMEOUT is used to set the number of retries that the
core, as a
         *      Master, will perform before abandoning a cycle. The default
value for
         *      RETRY_TIMEOUT is 0x80, which far exceeds the PCI 2.1 requirement
for new
         *      devices. A write of zero to the RETRY_TIMEOUT register disables this
         *      function to allow use with any non-compliant legacy devices that may
         *      execute more retries.
         *
         *      Writing zero to both these two registers will disable both
timeouts and
         *      *can* solve problems caused by devices that are slow to respond.
         */
        pci_write_config_byte(pdev, 0x40, 0);
        pci_write_config_byte(pdev, 0x41, 0);

Additional info on PCI config regesters for this chipset, anybody?



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