[Prism54-devel] USB driver
Feyd
feyd@seznam.cz
Sun, 4 Apr 2004 16:03:46 +0200
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Hi,
even the data sent to the dongle are the same (or at least appear to be)
as sent by the windows driver, the device doesnt boot. The only interrupt
it sends has status 0x80000000, not the desired 0x04. Im clueless. Could
please anyone with the dongle investigate?
Feyd
PS
Luis, could you please setup CVS repository for the usb driver?
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/* $Header: /var/lib/cvs/prism54-ng/ksrc/isl_38xx.h,v 1.24 2004/03/18 05:25:24 mcgrof Exp $
*
* Copyright (C) 2002 Intersil Americas Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef _ISL_38XX_H
#define _ISL_38XX_H
#include <linux/version.h>
#include <asm/io.h>
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,75))
#include <linux/device.h>
# define _REQ_FW_DEV_T struct device *
#else
# define _REQ_FW_DEV_T char *
#endif
#include <asm/byteorder.h>
#define ISL38XX_CB_RX_QSIZE 8
#define ISL38XX_CB_TX_QSIZE 32
/* ISL38XX Access Point Specific definitions */
#define ISL38XX_MAX_WDS_LINKS 8
/* ISL38xx Client Specific definitions */
#define ISL38XX_PSM_ACTIVE_STATE 0
#define ISL38XX_PSM_POWERSAVE_STATE 1
/* ISL38XX Host Interface Definitions */
#define ISL38XX_PCI_MEM_SIZE 0x02000
#define ISL38XX_MEMORY_WINDOW_SIZE 0x01000
#define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000
#define ISL38XX_WRITEIO_DELAY 10 /* in us */
#define ISL38XX_RESET_DELAY 50 /* in ms */
#define ISL38XX_WAIT_CYCLE 10 /* in 10ms */
#define ISL38XX_MAX_WAIT_CYCLES 10
/* PCI Memory Area */
#define ISL38XX_HARDWARE_REG 0x0000
#define ISL38XX_CARDBUS_CIS 0x0800
#define ISL38XX_DIRECT_MEM_WIN 0x1000
/* Hardware registers */
#define ISL38XX_DEV_INT_REG 0x0000
#define ISL38XX_INT_IDENT_REG 0x0010
#define ISL38XX_INT_ACK_REG 0x0014
#define ISL38XX_INT_EN_REG 0x0018
#define ISL38XX_GEN_PURP_COM_REG_1 0x0020
#define ISL38XX_GEN_PURP_COM_REG_2 0x0024
#define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1
#define ISL38XX_DIR_MEM_BASE_REG 0x0030
#define ISL38XX_CTRL_STAT_REG 0x0078
/* High end mobos queue up pci writes, the following
* is used to "read" from after a write to force flush */
#define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG
/**
* isl38xx_w32_flush - PCI iomem write helper
* @base: (host) memory base address of the device
* @val: 32bit value (host order) to write
* @offset: byte offset into @base to write value to
*
* This helper takes care of writing a 32bit datum to the
* specified offset into the device's pci memory space, and making sure
* the pci memory buffers get flushed by performing one harmless read
* from the %ISL38XX_PCI_POSTING_FLUSH offset.
*/
static inline void
isl38xx_w32_flush(void *base, u32 val, unsigned long offset)
{
writel(val, base + offset);
(void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
}
/* Device Interrupt register bits */
#define ISL38XX_DEV_INT_RESET 0x0001
#define ISL38XX_DEV_INT_UPDATE 0x0002
#define ISL38XX_DEV_INT_WAKEUP 0x0008
#define ISL38XX_DEV_INT_SLEEP 0x0010
/* Interrupt Identification/Acknowledge/Enable register bits */
#define ISL38XX_INT_IDENT_UPDATE 0x0002
#define ISL38XX_INT_IDENT_INIT 0x0004
#define ISL38XX_INT_IDENT_WAKEUP 0x0008
#define ISL38XX_INT_IDENT_SLEEP 0x0010
#define ISL38XX_INT_SOURCES 0x001E
/* Control/Status register bits */
#define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200
#define ISL38XX_CTRL_STAT_CLKRUN 0x00800000
#define ISL38XX_CTRL_STAT_RESET 0x10000000
#define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000
#define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000
#define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000
/* Control Block definitions */
#define ISL38XX_CB_RX_DATA_LQ 0
#define ISL38XX_CB_TX_DATA_LQ 1
#define ISL38XX_CB_RX_DATA_HQ 2
#define ISL38XX_CB_TX_DATA_HQ 3
#define ISL38XX_CB_RX_MGMTQ 4
#define ISL38XX_CB_TX_MGMTQ 5
#define ISL38XX_CB_QCOUNT 6
#define ISL38XX_CB_MGMT_QSIZE 4
#define ISL38XX_MIN_QTHRESHOLD 4 /* fragments */
/* Memory Manager definitions */
#define MGMT_FRAME_SIZE 1500 /* >= size struct obj_bsslist */
#define MGMT_TX_FRAME_COUNT 24 /* max 4 + spare 4 + 8 init */
#define MGMT_RX_FRAME_COUNT 24 /* 4*4 + spare 8 */
#define MGMT_FRAME_COUNT (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
#define CONTROL_BLOCK_SIZE 1024 /* should be enough */
#define PSM_FRAME_SIZE 1536
#define PSM_MINIMAL_STATION_COUNT 64
#define PSM_FRAME_COUNT PSM_MINIMAL_STATION_COUNT
#define PSM_BUFFER_SIZE PSM_FRAME_SIZE * PSM_FRAME_COUNT
#define MAX_TRAP_RX_QUEUE 4
#define HOST_MEM_BLOCK CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
/* Fragment package definitions */
#define FRAGMENT_FLAG_MF 0x0001
#define MAX_FRAGMENT_SIZE 1536
/* In monitor mode frames have a header. I don't know exactly how big those
* frame can be but I've never seen any frame bigger than 1584... :
*/
#define MAX_FRAGMENT_SIZE_RX 1600
typedef struct {
u32 address; /* physical address on host */
u16 size; /* packet size */
u16 flags; /* set of bit-wise flags */
} isl38xx_fragment;
struct isl38xx_cb {
u32 driver_curr_frag[ISL38XX_CB_QCOUNT];
u32 device_curr_frag[ISL38XX_CB_QCOUNT];
isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
};
typedef struct isl38xx_cb isl38xx_control_block;
/* determine number of entries currently in queue */
int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
void isl38xx_disable_interrupts(void *);
void isl38xx_enable_common_interrupts(void *);
void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
void *);
void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void *);
void isl38xx_trigger_device(int, void *);
void isl38xx_interface_reset(void *, dma_addr_t);
int isl38xx_upload_firmware(char *, _REQ_FW_DEV_T, void *, dma_addr_t);
#endif /* _ISL_38XX_H */
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/*
* NetChip 2280 high/full speed USB device controller.
* Unlike many such controllers, this one talks PCI.
*/
/*
* Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
* Copyright (C) 2003 David Brownell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*-------------------------------------------------------------------------*/
/* NET2280 MEMORY MAPPED REGISTERS
*
* The register layout came from the chip documentation, and the bit
* number definitions were extracted from chip specification.
*
* Use the shift operator ('<<') to build bit masks, with readl/writel
* to access the registers through PCI.
*/
/* main registers, BAR0 + 0x0000 */
struct net2280_regs {
// offset 0x0000
u32 devinit;
#define LOCAL_CLOCK_FREQUENCY 8
#define FORCE_PCI_RESET 7
#define PCI_ID 6
#define PCI_ENABLE 5
#define FIFO_SOFT_RESET 4
#define CFG_SOFT_RESET 3
#define PCI_SOFT_RESET 2
#define USB_SOFT_RESET 1
#define M8051_RESET 0
u32 eectl;
#define EEPROM_ADDRESS_WIDTH 23
#define EEPROM_CHIP_SELECT_ACTIVE 22
#define EEPROM_PRESENT 21
#define EEPROM_VALID 20
#define EEPROM_BUSY 19
#define EEPROM_CHIP_SELECT_ENABLE 18
#define EEPROM_BYTE_READ_START 17
#define EEPROM_BYTE_WRITE_START 16
#define EEPROM_READ_DATA 8
#define EEPROM_WRITE_DATA 0
u32 eeclkfreq;
u32 _unused0;
// offset 0x0010
u32 pciirqenb0; /* interrupt PCI master ... */
#define SETUP_PACKET_INTERRUPT_ENABLE 7
#define ENDPOINT_F_INTERRUPT_ENABLE 6
#define ENDPOINT_E_INTERRUPT_ENABLE 5
#define ENDPOINT_D_INTERRUPT_ENABLE 4
#define ENDPOINT_C_INTERRUPT_ENABLE 3
#define ENDPOINT_B_INTERRUPT_ENABLE 2
#define ENDPOINT_A_INTERRUPT_ENABLE 1
#define ENDPOINT_0_INTERRUPT_ENABLE 0
u32 pciirqenb1;
#define PCI_INTERRUPT_ENABLE 31
#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
#define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18
#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
#define GPIO_INTERRUPT_ENABLE 13
#define DMA_D_INTERRUPT_ENABLE 12
#define DMA_C_INTERRUPT_ENABLE 11
#define DMA_B_INTERRUPT_ENABLE 10
#define DMA_A_INTERRUPT_ENABLE 9
#define EEPROM_DONE_INTERRUPT_ENABLE 8
#define VBUS_INTERRUPT_ENABLE 7
#define CONTROL_STATUS_INTERRUPT_ENABLE 6
#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
#define RESUME_INTERRUPT_ENABLE 1
#define SOF_INTERRUPT_ENABLE 0
u32 cpu_irqenb0; /* ... or onboard 8051 */
#define SETUP_PACKET_INTERRUPT_ENABLE 7
#define ENDPOINT_F_INTERRUPT_ENABLE 6
#define ENDPOINT_E_INTERRUPT_ENABLE 5
#define ENDPOINT_D_INTERRUPT_ENABLE 4
#define ENDPOINT_C_INTERRUPT_ENABLE 3
#define ENDPOINT_B_INTERRUPT_ENABLE 2
#define ENDPOINT_A_INTERRUPT_ENABLE 1
#define ENDPOINT_0_INTERRUPT_ENABLE 0
u32 cpu_irqenb1;
#define CPU_INTERRUPT_ENABLE 31
#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
#define PCI_INTA_INTERRUPT_ENABLE 24
#define PCI_PME_INTERRUPT_ENABLE 23
#define PCI_SERR_INTERRUPT_ENABLE 22
#define PCI_PERR_INTERRUPT_ENABLE 21
#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
#define GPIO_INTERRUPT_ENABLE 13
#define DMA_D_INTERRUPT_ENABLE 12
#define DMA_C_INTERRUPT_ENABLE 11
#define DMA_B_INTERRUPT_ENABLE 10
#define DMA_A_INTERRUPT_ENABLE 9
#define EEPROM_DONE_INTERRUPT_ENABLE 8
#define VBUS_INTERRUPT_ENABLE 7
#define CONTROL_STATUS_INTERRUPT_ENABLE 6
#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
#define RESUME_INTERRUPT_ENABLE 1
#define SOF_INTERRUPT_ENABLE 0
// offset 0x0020
u32 _unused1;
u32 usbirqenb1;
#define USB_INTERRUPT_ENABLE 31
#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
#define PCI_INTA_INTERRUPT_ENABLE 24
#define PCI_PME_INTERRUPT_ENABLE 23
#define PCI_SERR_INTERRUPT_ENABLE 22
#define PCI_PERR_INTERRUPT_ENABLE 21
#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
#define GPIO_INTERRUPT_ENABLE 13
#define DMA_D_INTERRUPT_ENABLE 12
#define DMA_C_INTERRUPT_ENABLE 11
#define DMA_B_INTERRUPT_ENABLE 10
#define DMA_A_INTERRUPT_ENABLE 9
#define EEPROM_DONE_INTERRUPT_ENABLE 8
#define VBUS_INTERRUPT_ENABLE 7
#define CONTROL_STATUS_INTERRUPT_ENABLE 6
#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
#define RESUME_INTERRUPT_ENABLE 1
#define SOF_INTERRUPT_ENABLE 0
u32 irqstat0;
#define INTA_ASSERTED 12
#define SETUP_PACKET_INTERRUPT 7
#define ENDPOINT_F_INTERRUPT 6
#define ENDPOINT_E_INTERRUPT 5
#define ENDPOINT_D_INTERRUPT 4
#define ENDPOINT_C_INTERRUPT 3
#define ENDPOINT_B_INTERRUPT 2
#define ENDPOINT_A_INTERRUPT 1
#define ENDPOINT_0_INTERRUPT 0
u32 irqstat1;
#define POWER_STATE_CHANGE_INTERRUPT 27
#define PCI_ARBITER_TIMEOUT_INTERRUPT 26
#define PCI_PARITY_ERROR_INTERRUPT 25
#define PCI_INTA_INTERRUPT 24
#define PCI_PME_INTERRUPT 23
#define PCI_SERR_INTERRUPT 22
#define PCI_PERR_INTERRUPT 21
#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20
#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19
#define PCI_RETRY_ABORT_INTERRUPT 17
#define PCI_MASTER_CYCLE_DONE_INTERRUPT 16
#define GPIO_INTERRUPT 13
#define DMA_D_INTERRUPT 12
#define DMA_C_INTERRUPT 11
#define DMA_B_INTERRUPT 10
#define DMA_A_INTERRUPT 9
#define EEPROM_DONE_INTERRUPT 8
#define VBUS_INTERRUPT 7
#define CONTROL_STATUS_INTERRUPT 6
#define ROOT_PORT_RESET_INTERRUPT 4
#define SUSPEND_REQUEST_INTERRUPT 3
#define SUSPEND_REQUEST_CHANGE_INTERRUPT 2
#define RESUME_INTERRUPT 1
#define SOF_INTERRUPT 0
// offset 0x0030
u32 idxaddr;
u32 idxdata;
u32 fifoctl;
#define PCI_BASE2_RANGE 16
#define IGNORE_FIFO_AVAILABILITY 3
#define PCI_BASE2_SELECT 2
#define FIFO_CONFIGURATION_SELECT 0
u32 _unused2;
// offset 0x0040
u32 memaddr;
#define START 28
#define DIRECTION 27
#define FIFO_DIAGNOSTIC_SELECT 24
#define MEMORY_ADDRESS 0
u32 memdata0;
u32 memdata1;
u32 _unused3;
// offset 0x0050
u32 gpioctl;
#define GPIO3_LED_SELECT 12
#define GPIO3_INTERRUPT_ENABLE 11
#define GPIO2_INTERRUPT_ENABLE 10
#define GPIO1_INTERRUPT_ENABLE 9
#define GPIO0_INTERRUPT_ENABLE 8
#define GPIO3_OUTPUT_ENABLE 7
#define GPIO2_OUTPUT_ENABLE 6
#define GPIO1_OUTPUT_ENABLE 5
#define GPIO0_OUTPUT_ENABLE 4
#define GPIO3_DATA 3
#define GPIO2_DATA 2
#define GPIO1_DATA 1
#define GPIO0_DATA 0
u32 gpiostat;
#define GPIO3_INTERRUPT 3
#define GPIO2_INTERRUPT 2
#define GPIO1_INTERRUPT 1
#define GPIO0_INTERRUPT 0
} __attribute__ ((packed));
/* usb control, BAR0 + 0x0080 */
struct net2280_usb_regs {
// offset 0x0080
u32 stdrsp;
#define STALL_UNSUPPORTED_REQUESTS 31
#define SET_TEST_MODE 16
#define GET_OTHER_SPEED_CONFIGURATION 15
#define GET_DEVICE_QUALIFIER 14
#define SET_ADDRESS 13
#define ENDPOINT_SET_CLEAR_HALT 12
#define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11
#define GET_STRING_DESCRIPTOR_2 10
#define GET_STRING_DESCRIPTOR_1 9
#define GET_STRING_DESCRIPTOR_0 8
#define GET_SET_INTERFACE 6
#define GET_SET_CONFIGURATION 5
#define GET_CONFIGURATION_DESCRIPTOR 4
#define GET_DEVICE_DESCRIPTOR 3
#define GET_ENDPOINT_STATUS 2
#define GET_INTERFACE_STATUS 1
#define GET_DEVICE_STATUS 0
u32 prodvendid;
#define PRODUCT_ID 16
#define VENDOR_ID 0
u32 relnum;
u32 usbctl;
#define SERIAL_NUMBER_INDEX 16
#define PRODUCT_ID_STRING_ENABLE 13
#define VENDOR_ID_STRING_ENABLE 12
#define USB_ROOT_PORT_WAKEUP_ENABLE 11
#define VBUS_PIN 10
#define TIMED_DISCONNECT 9
#define SUSPEND_IMMEDIATELY 7
#define SELF_POWERED_USB_DEVICE 6
#define REMOTE_WAKEUP_SUPPORT 5
#define PME_POLARITY 4
#define USB_DETECT_ENABLE 3
#define PME_WAKEUP_ENABLE 2
#define DEVICE_REMOTE_WAKEUP_ENABLE 1
#define SELF_POWERED_STATUS 0
// offset 0x0090
u32 usbstat;
#define HIGH_SPEED 7
#define FULL_SPEED 6
#define GENERATE_RESUME 5
#define GENERATE_DEVICE_REMOTE_WAKEUP 4
u32 xcvrdiag;
#define FORCE_HIGH_SPEED_MODE 31
#define FORCE_FULL_SPEED_MODE 30
#define USB_TEST_MODE 24
#define LINE_STATE 16
#define TRANSCEIVER_OPERATION_MODE 2
#define TRANSCEIVER_SELECT 1
#define TERMINATION_SELECT 0
u32 setup0123;
u32 setup4567;
// offset 0x0090
u32 _unused0;
u32 ouraddr;
#define FORCE_IMMEDIATE 7
#define OUR_USB_ADDRESS 0
u32 ourconfig;
} __attribute__ ((packed));
/* pci control, BAR0 + 0x0100 */
struct net2280_pci_regs {
// offset 0x0100
u32 pcimstctl;
#define PCI_ARBITER_PARK_SELECT 13
#define PCI_MULTI LEVEL_ARBITER 12
#define PCI_RETRY_ABORT_ENABLE 11
#define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10
#define DMA_READ_MULTIPLE_ENABLE 9
#define DMA_READ_LINE_ENABLE 8
#define PCI_MASTER_COMMAND_SELECT 6
#define MEM_READ_OR_WRITE 0
#define IO_READ_OR_WRITE 1
#define CFG_READ_OR_WRITE 2
#define PCI_MASTER_START 5
#define PCI_MASTER_READ_WRITE 4
#define PCI_MASTER_WRITE 0
#define PCI_MASTER_READ 1
#define PCI_MASTER_BYTE_WRITE_ENABLES 0
u32 pcimstaddr;
u32 pcimstdata;
u32 pcimststat;
#define PCI_ARBITER_CLEAR 2
#define PCI_EXTERNAL_ARBITER 1
#define PCI_HOST_MODE 0
} __attribute__ ((packed));
/* dma control, BAR0 + 0x0180 ... array of four structs like this,
* for channels 0..3. see also struct net2280_dma: descriptor
* that can be loaded into some of these registers.
*/
struct net2280_dma_regs { /* [11.7] */
// offset 0x0180, 0x01a0, 0x01c0, 0x01e0,
u32 dmactl;
#define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25
#define DMA_CLEAR_COUNT_ENABLE 21
#define DESCRIPTOR_POLLING_RATE 19
#define POLL_CONTINUOUS 0
#define POLL_1_USEC 1
#define POLL_100_USEC 2
#define POLL_1_MSEC 3
#define DMA_VALID_BIT_POLLING_ENABLE 18
#define DMA_VALID_BIT_ENABLE 17
#define DMA_SCATTER_GATHER_ENABLE 16
#define DMA_OUT_AUTO_START_ENABLE 4
#define DMA_PREEMPT_ENABLE 3
#define DMA_FIFO_VALIDATE 2
#define DMA_ENABLE 1
#define DMA_ADDRESS_HOLD 0
u32 dmastat;
#define DMA_SCATTER_GATHER_DONE_INTERRUPT 25
#define DMA_TRANSACTION_DONE_INTERRUPT 24
#define DMA_ABORT 1
#define DMA_START 0
u32 _unused0 [2];
// offset 0x0190, 0x01b0, 0x01d0, 0x01f0,
u32 dmacount;
#define VALID_BIT 31
#define DMA_DIRECTION 30
#define DMA_DONE_INTERRUPT_ENABLE 29
#define END_OF_CHAIN 28
#define DMA_BYTE_COUNT_MASK ((1<<24)-1)
#define DMA_BYTE_COUNT 0
u32 dmaaddr;
u32 dmadesc;
u32 _unused1;
} __attribute__ ((packed));
/* dedicated endpoint registers, BAR0 + 0x0200 */
struct net2280_dep_regs { /* [11.8] */
// offset 0x0200, 0x0210, 0x220, 0x230, 0x240
u32 dep_cfg;
// offset 0x0204, 0x0214, 0x224, 0x234, 0x244
u32 dep_rsp;
u32 _unused [2];
} __attribute__ ((packed));
/* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
* like this, for ep0 then the configurable endpoints A..F
* ep0 reserved for control; E and F have only 64 bytes of fifo
*/
struct net2280_ep_regs { /* [11.9] */
// offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0
u32 ep_cfg;
#define ENDPOINT_BYTE_COUNT 16
#define ENDPOINT_ENABLE 10
#define ENDPOINT_TYPE 8
#define ENDPOINT_DIRECTION 7
#define ENDPOINT_NUMBER 0
u32 ep_rsp;
#define SET_NAK_OUT_PACKETS 15
#define SET_EP_HIDE_STATUS_PHASE 14
#define SET_EP_FORCE_CRC_ERROR 13
#define SET_INTERRUPT_MODE 12
#define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11
#define SET_NAK_OUT_PACKETS_MODE 10
#define SET_ENDPOINT_TOGGLE 9
#define SET_ENDPOINT_HALT 8
#define CLEAR_NAK_OUT_PACKETS 7
#define CLEAR_EP_HIDE_STATUS_PHASE 6
#define CLEAR_EP_FORCE_CRC_ERROR 5
#define CLEAR_INTERRUPT_MODE 4
#define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3
#define CLEAR_NAK_OUT_PACKETS_MODE 2
#define CLEAR_ENDPOINT_TOGGLE 1
#define CLEAR_ENDPOINT_HALT 0
u32 ep_irqenb;
#define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6
#define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5
#define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3
#define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2
#define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1
#define DATA_IN_TOKEN_INTERRUPT_ENABLE 0
u32 ep_stat;
#define FIFO_VALID_COUNT 24
#define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22
#define TIMEOUT 21
#define USB_STALL_SENT 20
#define USB_IN_NAK_SENT 19
#define USB_IN_ACK_RCVD 18
#define USB_OUT_PING_NAK_SENT 17
#define USB_OUT_ACK_SENT 16
#define FIFO_OVERFLOW 13
#define FIFO_UNDERFLOW 12
#define FIFO_FULL 11
#define FIFO_EMPTY 10
#define FIFO_FLUSH 9
#define SHORT_PACKET_OUT_DONE_INTERRUPT 6
#define SHORT_PACKET_TRANSFERRED_INTERRUPT 5
#define NAK_OUT_PACKETS 4
#define DATA_PACKET_RECEIVED_INTERRUPT 3
#define DATA_PACKET_TRANSMITTED_INTERRUPT 2
#define DATA_OUT_PING_TOKEN_INTERRUPT 1
#define DATA_IN_TOKEN_INTERRUPT 0
// offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0
u32 ep_avail;
u32 ep_data;
u32 _unused0 [2];
} __attribute__ ((packed));
--Multipart=_Sun__4_Apr_2004_16_03_46_+0200_t4U0QFKPIx=mIm5z
Content-Type: text/x-chdr;
name="prism54_usb.h"
Content-Disposition: attachment;
filename="prism54_usb.h"
Content-Transfer-Encoding: 7bit
/*
* Prism54 USB driver
T: Bus=01 Lev=01 Prnt=01 Port=03 Cnt=01 Dev#= 2 Spd=480 MxCh= 0
D: Ver= 2.00 Cls=ff(vend.) Sub=00 Prot=00 MxPS=64 #Cfgs= 1
P: Vendor=5041 ProdID=2234 Rev= 2.02
C:* #Ifs= 1 Cfg#= 1 Atr=80 MxPwr=500mA
I: If#= 0 Alt= 0 #EPs=11 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none)
E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=8d(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=0d(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=8e(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=0e(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=8f(I) Atr=03(Int.) MxPS= 4 Ivl=125us
*/
#include "net2280.h"
//#undef CONFIG_USB_DEBUG
//#define CONFIG_USB_DEBUG y
#ifdef CONFIG_USB_DEBUG
#define p54u_dbg(format, arg...) if(debug > 1) printk(format "\n" ,##arg)
#else
#define p54u_dbg(format, arg...)
#endif
#define p54u_info(format, arg...) if(debug) printk(KERN_INFO __FILE__ ": " format "\n" , ##arg)
#define p54u_warn(format, arg...) printk(KERN_WARN __FILE__ ": " format "\n" , ##arg)
#define p54u_err(format, arg...) printk(KERN_ERR __FILE__ ": " format "\n" ,##arg)
#define p54u_time(arg...) 0LL
//#define p54u_time(arg...) (get_jiffies_64(##arg) - p54u->time)
#define P54U_TX_TIMEOUT (2*HZ)
#define P54U_REG_WSIZE (sizeof(struct p54u_reg))
#define P54U_REG_RSIZE (P54U_REG_WSIZE - (sizeof(u32)))
#define P54U_PORT_BRG 0x0010
#define P54U_PORT_BRG_CFG 0x0000
#define P54U_PORT_DEV 0x0800
#define P54U_PORT_DEV_CFG 0x0880
#define P54U_PORT_U16 0x0003
#define P54U_PORT_U32 0x000f
#define P54U_PORT_BRG_U32 (P54U_PORT_BRG | P54U_PORT_U32)
#define P54U_PORT_BRG_CFG_U32 (P54U_PORT_BRG_CFG | P54U_PORT_U32)
#define P54U_PORT_BRG_CFG_U16 (P54U_PORT_BRG_CFG | P54U_PORT_U16)
#define P54U_PORT_DEV_U32 (P54U_PORT_DEV | P54U_PORT_U32)
#define P54U_PORT_DEV_CFG_U32 (P54U_PORT_DEV_CFG | P54U_PORT_U32)
#define P54U_PORT_DEV_CFG_U16 (P54U_PORT_DEV_CFG | P54U_PORT_U16)
/* pci */
#define NET2280_BASE 0x10000000
#define NET2280_BASE2 0x20000000
/* gpio */
#define P54U_BRG_POWER_UP (1 << GPIO0_DATA)
#define P54U_BRG_POWER_DOWN (1 << GPIO1_DATA)
/* devinit */
#define NET2280_CLK_4Mhz (15 << LOCAL_CLOCK_FREQUENCY)
#define NET2280_CLK_30Mhz (2 << LOCAL_CLOCK_FREQUENCY)
#define NET2280_CLK_60Mhz (1 << LOCAL_CLOCK_FREQUENCY)
#define NET2280_CLK_STOP (0 << LOCAL_CLOCK_FREQUENCY)
#define NET2280_PCI_ENABLE (1 << PCI_ENABLE)
#define NET2280_PCI_SOFT_RESET (1 << PCI_SOFT_RESET)
/* enpoints */
#define NET2280_CLEAR_NAK_OUT_PACKETS_MODE (1 << CLEAR_NAK_OUT_PACKETS_MODE)
#define NET2280_FIFO_FLUSH (1 << FIFO_FLUSH)
/* irq */
#define NET2280_USB_INTERRUPT_ENABLE (1 << USB_INTERRUPT_ENABLE)
#define NET2280_PCI_INTA_INTERRUPT (1 << PCI_INTA_INTERRUPT)
#define NET2280_PCI_INTA_INTERRUPT_ENABLE (1 << PCI_INTA_INTERRUPT_ENABLE)
/* registers */
#define NET2280_DEVINIT 0x00
#define NET2280_USBIRQENB1 0x24
#define NET2280_IRQSTAT1 0x2c
#define NET2280_GPIOCTL 0x50
#define NET2280_RELNUM 0x88
#define NET2280_EPA_RSP 0x324
#define NET2280_EPA_STAT 0x32c
#define NET2280_EPB_STAT 0x34c
#define NET2280_EPC_RSP 0x364
#define NET2280_EPC_STAT 0x36c
#define NET2280_EPD_STAT 0x38c
#define P54U_DEV_BASE 0x40000000
#define P54U_TRDY_TIMEOUT 0x40
#define P54U_RETRY_TIMEOUTG 0x41
#define P54U_IMAGE_FILE "isl3890"
//#define P54U_MAX_FRAME_SIZE 16384
#define P54U_MAX_FRAME_SIZE 4096
//#define P54U_QUEUE_LEN 16
#define P54U_QUEUE_LEN 2
#define P54U_FW_BLOCK 512
#define P54U_INIT_BLOCK 0x03fc
//#define P54U_INIT_BLOCK 490
#define p54u_brg_writel(dev, addr, val) p54u_reg_rw(dev, 1, P54U_PIPE_BRG, P54U_PORT_BRG_U32, addr, val)
#define p54u_pcicfg_brg_writel(dev, addr, val) p54u_reg_rw(dev, 1, P54U_PIPE_BRG, P54U_PORT_BRG_CFG_U32, addr, val)
#define p54u_pcicfg_brg_writew(dev, addr, val) p54u_reg_rw(dev, 1, P54U_PIPE_BRG, P54U_PORT_BRG_CFG_U16, addr, (val & 0xffff))
#define p54u_dev_writel(dev, reg, val) p54u_reg_rw(dev, 1, P54U_PIPE_DEV, P54U_PORT_DEV_U32, (P54U_DEV_BASE | reg), val)
#define p54u_pcicfg_dev_writel(dev, addr, val) p54u_reg_rw(dev, 1, P54U_PIPE_DEV, P54U_PORT_DEV_CFG_U32, addr, val)
#define p54u_pcicfg_dev_writew(dev, addr, val) p54u_reg_rw(dev, 1, P54U_PIPE_DEV, P54U_PORT_DEV_CFG_U16, addr, (val & 0xffff))
#define p54u_brg_readl(dev, addr) p54u_reg_rw(dev, 0, P54U_PIPE_BRG, P54U_PORT_BRG_U32, addr, 0)
#define p54u_pcicfg_brg_readl(dev, addr) p54u_reg_rw(dev, 0, P54U_PIPE_BRG, P54U_PORT_BRG_CFG_U32, addr, 0)
#define p54u_pcicfg_brg_readw(dev, addr) (p54u_reg_rw(dev, 0, P54U_PIPE_BRG, P54U_PORT_BRG_CFG_U16, addr, 0) & 0xffff)
#define p54u_dev_readl(dev, reg) p54u_reg_rw(dev, 0, P54U_PIPE_DEV, P54U_PORT_DEV_U32, (P54U_DEV_BASE | reg), 0)
#define p54u_pcicfg_dev_readl(dev, addr) p54u_reg_rw(dev, 0, P54U_PIPE_DEV, P54U_PORT_DEV_CFG_U32, addr, 0)
#define p54u_pcicfg_dev_readw(dev, addr) (p54u_reg_rw(dev, 0, P54U_PIPE_DEV, P54U_PORT_DEV_CFG_U16, addr, 0) & 0xffff)
enum p54u_pipe_addr {
P54U_PIPE_DATA = 0x01,
P54U_PIPE_MGMT = 0x02,
P54U_PIPE_3 = 0x03,
P54U_PIPE_4 = 0x04,
P54U_PIPE_BRG = 0x0d,
P54U_PIPE_DEV = 0x0e,
P54U_PIPE_INT = 0x0f,
};
enum p54u_pipe_index {
P54U_TX_DATA,
P54U_TX_MGMT,
P54U_TX_BRG,
P54U_TX_DEV,
P54U_RX_DATA,
P54U_RX_MGMT,
P54U_RX_3,
P54U_RX_4,
P54U_RX_BRG,
P54U_RX_DEV,
P54U_RX_INT,
P54U_PIPES,
};
struct p54u_reg {
u16 port;
u32 addr;
u32 val;
} __attribute__ ((packed));
struct p54u_mgmt_tx {
u32 magic1;
u32 magic2;
u32 magic3;
u16 pos;
u16 len;
} __attribute__ ((packed));
struct p54u_mgmt_rx {
u16 len;
u16 pos;
u32 magic1;
u32 magic2;
u32 magic3;
struct p54u_mgmt_tx id;
} __attribute__ ((packed));
struct p54u_pipe_desc {
u8 addr; /* the address of the endpoint */
u8 type; /* the transfer type of the endpoint */
size_t p_size; /* the size of the packet */
void (*callback)(struct urb *urb, struct pt_regs *regs);
};
struct p54u_pipe {
struct urb **urb; /* the urb used to send data */
void **buf; /* the buffer */
size_t *size; /* the size of the buffer */
int len; /* the length of the ringbufer */
int head;
int tail;
atomic_t busy; /* true if urb is busy */
wait_queue_head_t wqh;
struct completion comp; /* wait for the operation to finish */
int done;
u8 addr; /* the address of the endpoint */
u8 type; /* the transfer type of the endpoint */
size_t pkt_size; /* the size of the packet */
};
/* Structure to hold all of our device specific stuff */
struct p54u {
struct usb_device *usbdev; /* save off the usb device pointer */
struct usb_interface *interface; /* save off the usb device pointer */
struct net_device *netdev;
int running;
int err;
struct workqueue_struct *queue;
struct work *boot;
struct completion *comp;
struct p54u_pipe data_tx;
struct p54u_pipe data_rx;
struct p54u_pipe mgmt_tx;
struct p54u_pipe mgmt_rx;
struct p54u_pipe int_rx;
struct semaphore disconnect_sem; /* prevent races between open() and disconnect() */
const struct firmware *fw_entry;
u64 time;
int pending;
};
extern int load_fw;
extern int debug;
extern const char dummy_mac[ETH_ALEN];
int p54u_setup_net(struct net_device *netdev);
int p54u_boot(struct net_device *netdev);
int p54u_shutdown(struct net_device *netdev);
void p54u_mdelay(int ms);
u32 p54u_reg_rw(struct net_device *netdev, int write, int ep, int port, u32 addr, u32 val);
int p54u_readi(struct net_device *netdev);
void p54u_int_rx_cb(struct urb *urb, struct pt_regs *p);
void p54u_data_rx_cb(struct urb *urb, struct pt_regs *p);
void p54u_mgmt_rx_cb(struct urb *urb, struct pt_regs *p);
int p54u_wait_int(struct net_device *netdev);
int p54u_bulk_msg(struct net_device *netdev, unsigned int ep, void *data, int len);
void p54u_data_debug(struct net_device *netdev, unsigned int ep, void *_data, int len);
--Multipart=_Sun__4_Apr_2004_16_03_46_+0200_t4U0QFKPIx=mIm5z
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--Multipart=_Sun__4_Apr_2004_16_03_46_+0200_t4U0QFKPIx=mIm5z
Content-Type: text/x-csrc;
name="usb_init.c"
Content-Disposition: attachment;
filename="usb_init.c"
Content-Transfer-Encoding: 7bit
/*
* Prism54 USB driver
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/smp_lock.h>
#include <linux/completion.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/usb.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <asm/uaccess.h>
#include "prism54_usb.h"
#include "isl_38xx.h"
#ifdef CONFIG_USB_DEBUG
int debug = 2;
#else
int debug;
#endif
int load_fw;
static const char driver_name[] = "prism54_usb";
static const struct usb_device_id p54u_table[] = {
{USB_DEVICE(0x5041, 0x2234)}, /* Linksys WUSB54G */
{}
};
static const struct p54u_pipe_desc p54u_pipes[] = {
{ P54U_PIPE_DATA, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_MGMT, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_BRG, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_DEV, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_DATA | USB_DIR_IN, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_MGMT | USB_DIR_IN, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_3 | USB_DIR_IN, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_4 | USB_DIR_IN, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_BRG | USB_DIR_IN, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_DEV | USB_DIR_IN, USB_ENDPOINT_XFER_BULK },
{ P54U_PIPE_INT | USB_DIR_IN, USB_ENDPOINT_XFER_INT },
};
static const char p54u_mgmt_0c[16] = {
0x6c, 0x06, 0x02, 0x00, 0x0c, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const char p54u_mgmt_30[16] = {
0x6c, 0x06, 0x02, 0x00, 0x30, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
MODULE_DESCRIPTION("Prism54 USB Driver");
MODULE_AUTHOR("Feyd <feyd@seznam.cz>");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(usb, p54u_table);
MODULE_PARM(debug, "i");
MODULE_PARM(load_fw, "i");
MODULE_PARM_DESC(debug, "Debug enabled or not");
MODULE_PARM_DESC(load_fw, "Load firmware on probe (1) or open (0)");
static int p54u_reset_usb(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
int err = 0;
u32 reg;
// return 0;
p54u_info("%s: Reset USB device.\n", netdev->name);
err = usb_reset_device(usbdev);
if(err) {
p54u_err("%s: Reset USB device failed.\n", netdev->name);
return err;
}
// p54u_mdelay(200);
p54u_info("%s: Reset USB device done.\n", netdev->name);
return 0;
do_err:
p54u_err("%s: Reset USB device failed.\n", netdev->name);
return err;
}
static void p54u_free_pipe(struct net_device *netdev, struct p54u_pipe *pipe)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
int i;
p54u_info("Freeing pipe.\n");
if(!pipe->buf) {
p54u_info("pipe->buf == NULL\n");
goto do_free_urb;
}
if(!pipe->urb) {
p54u_info("pipe->urb == NULL\n");
goto do_free_size;
}
if(!pipe->size) {
p54u_info("pipe->size == NULL\n");
goto do_clear;
}
for(i = 0; i < pipe->len; i++) {
if(pipe->urb[i]) {
/* FIXME: unlink the busy one */
if(pipe->buf[i]) {
usb_buffer_free(usbdev, pipe->size[i], pipe->buf[i], pipe->urb[i]->transfer_dma);
} else {
p54u_info("pipe->buf[%i] == NULL\n", i);
}
usb_free_urb(pipe->urb[i]);
} else {
p54u_info("pipe->urb[%i] == NULL\n", i);
}
}
kfree(pipe->buf);
do_free_urb:
if(pipe->urb) {
kfree(pipe->urb);
} else {
p54u_info("pipe->urb == NULL\n");
}
do_free_size:
if(pipe->size) {
kfree(pipe->size);
} else {
p54u_info("pipe->size == NULL\n");
}
do_clear:
p54u_info("Clear the memory.\n");
memset(pipe, 0, sizeof(*pipe));
p54u_info("Freeing pipe done.\n");
return;
}
static void p54u_free_buffers(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
p54u_free_pipe(netdev, &p54u->data_tx);
p54u_free_pipe(netdev, &p54u->data_rx);
p54u_free_pipe(netdev, &p54u->mgmt_tx);
p54u_free_pipe(netdev, &p54u->mgmt_rx);
p54u_free_pipe(netdev, &p54u->int_rx);
return;
}
static int p54u_alloc_pipe(struct net_device *netdev, struct usb_endpoint_descriptor *desc, struct p54u_pipe *pipe, usb_complete_t callback)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
int err, i, p, e;
if(!pipe)
return 0;
p54u_info("%s: Allocate pipe %02x.\n", netdev->name, desc->bEndpointAddress);
pipe->pkt_size = desc->wMaxPacketSize;
pipe->type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
pipe->addr = desc->bEndpointAddress;
pipe->len = P54U_QUEUE_LEN;
pipe->size = kmalloc(sizeof(*pipe->size) * pipe->len, GFP_KERNEL);
if(!pipe->size) {
p54u_info("Failed to allocate pipe->size\n");
goto do_enomem;
} else {
p54u_info("pipe->size == %p\n", pipe->size);
}
memset(pipe->size, 0, sizeof(*pipe->size) * pipe->len);
pipe->urb = kmalloc(sizeof(*pipe->urb) * pipe->len, GFP_KERNEL);
if(!pipe->urb) {
p54u_info("Failed to allocate pipe->urb\n");
goto do_enomem;
} else {
p54u_info("pipe->urb == %p\n", pipe->urb);
}
memset(pipe->urb, 0, sizeof(*pipe->urb) * pipe->len);
pipe->buf = kmalloc(sizeof(*pipe->buf) * pipe->len, GFP_KERNEL);
if(!pipe->buf) {
p54u_info("Failed to allocate pipe->buf\n");
goto do_enomem;
} else {
p54u_info("pipe->buf == %p\n", pipe->buf);
}
memset(pipe->buf, 0, sizeof(*pipe->buf) * pipe->len);
p54u_info("%s: Allocate buffers.\n", netdev->name);
for(i = 0; i < pipe->len; i++) {
pipe->size[i] = P54U_MAX_FRAME_SIZE;
if(pipe->type == USB_ENDPOINT_XFER_INT) {
pipe->size[i] = 4;
}
p54u_info("pipe->size [%i] = %i\n", i, pipe->size[i]);
pipe->urb[i] = usb_alloc_urb(0, GFP_KERNEL);
if(!pipe->urb[i]) {
p54u_info("Failed to allocate pipe->urb[%i]\n", i);
goto do_enomem;
} else {
p54u_info("pipe->urb[%i] == %p\n", i, pipe->urb[i]);
}
pipe->urb[i]->transfer_flags = (URB_NO_TRANSFER_DMA_MAP | URB_ASYNC_UNLINK);
pipe->buf[i] = usb_buffer_alloc(usbdev, pipe->size[i], GFP_KERNEL, &pipe->urb[i]->transfer_dma);
if(!pipe->buf[i]) {
p54u_info("Failed to allocate pipe->buf[%i]\n", i);
goto do_enomem;
} else {
p54u_info("pipe->buf[%i] == %p\n", i, pipe->buf[i]);
}
e = pipe->addr & USB_ENDPOINT_NUMBER_MASK;
p54u_info("pipe->addr = %i\n", e);
// e = pipe->addr;
switch(pipe->type) {
case USB_ENDPOINT_XFER_BULK:
p = pipe->addr & USB_DIR_IN ? usb_rcvbulkpipe(usbdev, e) : usb_sndbulkpipe(usbdev, e);
usb_fill_bulk_urb(pipe->urb[i], usbdev, p, pipe->buf[i], pipe->size[i], callback, netdev);
case USB_ENDPOINT_XFER_INT:
p = usb_rcvintpipe(usbdev, e);
usb_fill_int_urb(pipe->urb[i], usbdev, p, pipe->buf[i], pipe->size[i], callback, netdev, 6);
// usb_fill_int_urb(pipe->urb[i], usbdev, p, pipe->buf[i], pipe->size[i], callback, netdev, HZ / 4);
// p = pipe->addr & USB_DIR_IN ? usb_rcvbulkpipe(usbdev, e) : usb_sndbulkpipe(usbdev, e);
// usb_fill_bulk_urb(pipe->urb[i], usbdev, p, pipe->buf[i], pipe->size[i], callback, netdev);
}
init_completion(&pipe->comp);
}
p54u_info("%s: Allocate pipe done.\n", netdev->name);
return 0;
do_enomem:
p54u_info("%s: Not enough memory.\n", netdev->name);
err = -ENOMEM;
do_err:
p54u_info("%s: Allocate pipe failed.\n", netdev->name);
return err;
}
static int p54u_alloc_buffers(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
struct usb_interface *interface = p54u->interface;
struct usb_host_interface *iface_desc = &interface->altsetting[0];
struct usb_endpoint_descriptor *desc;
struct p54u_pipe *pipe;
int err = 0, i;
p54u_info("%s: Setup USB structures.\n", netdev->name);
for(i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
desc = &iface_desc->endpoint[i].desc;
switch(desc->bEndpointAddress) {
case P54U_PIPE_DATA:
err = p54u_alloc_pipe(netdev, desc, &p54u->data_tx, NULL);
break;
case P54U_PIPE_MGMT:
err = p54u_alloc_pipe(netdev, desc, &p54u->mgmt_tx, NULL);
break;
case P54U_PIPE_DATA | USB_DIR_IN:
err = p54u_alloc_pipe(netdev, desc, &p54u->data_rx, p54u_data_rx_cb);
break;
case P54U_PIPE_MGMT | USB_DIR_IN:
err = p54u_alloc_pipe(netdev, desc, &p54u->mgmt_rx, p54u_mgmt_rx_cb);
break;
case P54U_PIPE_INT | USB_DIR_IN:
err = p54u_alloc_pipe(netdev, desc , &p54u->int_rx, p54u_int_rx_cb);
break;
default:
break;
}
if(err)
goto do_err;
}
p54u_info("%s: Setup USB structures successful.\n", netdev->name);
return 0;
do_err:
p54u_info("%s: Setup USB structures failed: %i\n", netdev->name, err);
p54u_free_buffers(netdev);
return err;
}
static int p54u_reset_dev(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
u32 reg, revision;
int err;
p54u_info("%s: Reset device.\n", netdev->name);
/* Bridge */
/* Reset the usb<->pci bridge */
p54u_dbg("%s: Reset bridge\n", netdev->name);
reg = p54u_brg_readl(netdev, NET2280_GPIOCTL);
//reg = 0x3e;
//reg |= 0x3e;
p54u_brg_writel(netdev, NET2280_GPIOCTL, (reg | P54U_BRG_POWER_DOWN) & ~P54U_BRG_POWER_UP);
if(p54u->err)
goto do_err;
p54u_mdelay(100);
p54u_brg_writel(netdev, NET2280_GPIOCTL, (reg | P54U_BRG_POWER_UP) & ~P54U_BRG_POWER_DOWN);
if(p54u->err)
goto do_err;
p54u_dbg("%s: Reset bridge done\n", netdev->name);
p54u_mdelay(100);
/* Magic */
p54u_dbg("%s: Magic 1\n", netdev->name);
p54u_brg_writel(netdev, NET2280_DEVINIT, NET2280_CLK_30Mhz | NET2280_PCI_ENABLE | NET2280_PCI_SOFT_RESET);
if(p54u->err)
goto do_err;
p54u_dbg("%s: Magic 1 done\n", netdev->name);
p54u_mdelay(20);
/* Enable mmio and busmaster on the bridge */
p54u_dbg("%s: Setup bridge pci resources\n", netdev->name);
p54u_pcicfg_brg_writew(netdev, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Set base address 0 */
p54u_pcicfg_brg_writel(netdev, PCI_BASE_ADDRESS_0, NET2280_BASE);
/* Set PCI_STATUS_REC_MASTER_ABORT) (why?) */
reg = p54u_pcicfg_brg_readw(netdev, PCI_STATUS);
p54u_pcicfg_brg_writew(netdev, PCI_STATUS, (reg | PCI_STATUS_REC_MASTER_ABORT));
/* Read revision? */
revision = p54u_brg_readl(netdev, NET2280_RELNUM);
p54u_dbg("%s: Setup bridge pci resources done\n", netdev->name);
/* Magic */
p54u_dbg("%s: Magic 2\n", netdev->name);
p54u_brg_writel(netdev, NET2280_EPA_RSP, NET2280_CLEAR_NAK_OUT_PACKETS_MODE);
p54u_brg_writel(netdev, NET2280_EPC_RSP, NET2280_CLEAR_NAK_OUT_PACKETS_MODE);
p54u_dbg("%s: Magic 2 done\n", netdev->name);
/* Set base address 2 */
p54u_dbg("%s: Setup bridge base addr 2\n", netdev->name);
p54u_pcicfg_brg_writel(netdev, PCI_BASE_ADDRESS_2, NET2280_BASE2);
p54u_dbg("%s: Setup bridge base addr 2 done\n", netdev->name);
/* Device */
/* Enable mmio and busmaster on the device */
p54u_dbg("%s: Setup device pci resources\n", netdev->name);
p54u_pcicfg_dev_writew(netdev, PCI_COMMAND | 0x10000, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
// p54u_pcicfg_dev_writew(netdev, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Set TRDY_TIMEOUT and RETRY_TIMEOUT to 0 */
p54u_pcicfg_dev_writew(netdev, P54U_TRDY_TIMEOUT | 0x10000, 0);
// p54u_pcicfg_dev_writew(netdev, P54U_TRDY_TIMEOUT, 0);
/* Set base address 0 */
p54u_pcicfg_dev_writel(netdev, PCI_BASE_ADDRESS_0 | 0x10000, P54U_DEV_BASE);
// p54u_pcicfg_dev_writel(netdev, PCI_BASE_ADDRESS_0, P54U_DEV_BASE);
p54u_dbg("%s: Setup device pci resources done\n", netdev->name);
/* Magic */
p54u_dbg("%s: Magic 3\n", netdev->name);
p54u_brg_writel(netdev, NET2280_USBIRQENB1, 0);
// p54u_brg_writel(netdev, NET2280_USBIRQENB1, NET2280_PCI_INTA_INTERRUPT_ENABLE | NET2280_USB_INTERRUPT_ENABLE);
p54u_brg_writel(netdev, NET2280_IRQSTAT1, NET2280_PCI_INTA_INTERRUPT);
p54u_dbg("%s: Magic 3 done\n", netdev->name);
/* Assert wakeup */
p54u_dbg("%s: Assert device\n", netdev->name);
p54u_dev_writel(netdev, ISL38XX_DEV_INT_REG, ISL38XX_DEV_INT_WAKEUP);
if(p54u->err)
goto do_err;
p54u_mdelay(20);
/* Assert something unknown */
p54u_dev_writel(netdev, ISL38XX_DEV_INT_REG, 0x20);
if(p54u->err)
goto do_err;
p54u_dbg("%s: Assert device done\n", netdev->name);
p54u_mdelay(20);
/* Reset the device */
p54u_dbg("%s: Reset device\n", netdev->name);
reg = p54u_dev_readl(netdev, ISL38XX_CTRL_STAT_REG);
// reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT);
reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT | ISL38XX_CTRL_STAT_CLKRUN);
p54u_dev_writel(netdev, ISL38XX_CTRL_STAT_REG, reg);
p54u_dev_writel(netdev, ISL38XX_CTRL_STAT_REG, reg | ISL38XX_CTRL_STAT_RESET);
p54u_dev_writel(netdev, ISL38XX_CTRL_STAT_REG, reg);
if(p54u->err)
goto do_err;
p54u_dbg("%s: Reset device done\n", netdev->name);
p54u_mdelay(100);
p54u_dbg("%s: Disable irq\n", netdev->name);
p54u_dev_writel(netdev, ISL38XX_INT_EN_REG, 0);
// p54u_dev_writel(netdev, ISL38XX_INT_EN_REG, 0x00004004);
p54u_dbg("%s: Disable irq done\n", netdev->name);
// p54u_mdelay(50);
/* Ack the irqs */
p54u_dbg("%s: Ack irq\n", netdev->name);
reg = p54u_dev_readl(netdev, ISL38XX_INT_IDENT_REG);
p54u_dev_writel(netdev, ISL38XX_INT_ACK_REG, reg);
if(p54u->err)
goto do_err;
p54u_dbg("%s: Ack done\n", netdev->name);
/* Magic */
p54u_dbg("%s: Magic 4\n", netdev->name);
p54u_brg_writel(netdev, NET2280_EPA_STAT, NET2280_FIFO_FLUSH);
p54u_brg_writel(netdev, NET2280_EPB_STAT, NET2280_FIFO_FLUSH);
p54u_brg_writel(netdev, NET2280_EPC_STAT, NET2280_FIFO_FLUSH);
p54u_brg_writel(netdev, NET2280_EPD_STAT, NET2280_FIFO_FLUSH);
p54u_brg_writel(netdev, NET2280_EPA_STAT, NET2280_FIFO_FLUSH);
p54u_dbg("%s: Magic 4 done\n", netdev->name);
p54u_info("%s: Reset device done.\n", netdev->name);
return 0;
do_err:
p54u_err("%s: Reset error: %i\n", netdev->name, p54u->err);
err = p54u->err;
p54u->err = 0;
return err;
}
static int p54u_load_firmware(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
unsigned int pipe;
u32 reg;
void *data;
size_t len;
int err, i, j, k, l;
u64 t, t1, t2;
char *rcv;
p54u_info("%s: Load firmware.\n", netdev->name);
/* Firmware */
pipe = usb_sndbulkpipe(usbdev, P54U_PIPE_DATA);
data = p54u->fw_entry->data;
i = p54u->fw_entry->size;
j = 0;
while(i > 0) {
len = i > P54U_FW_BLOCK ? P54U_FW_BLOCK : i;
t1 = p54u_time();
p54u->err = usb_bulk_msg(usbdev, pipe, data, len, &len, HZ);
t2 = p54u_time();
t = t2 - t1;
p54u_data_debug(netdev, P54U_PIPE_DATA, data, len);
if(p54u->err) {
p54u_dbg("%s: Error writing firmware block: writen %i of %i.\n", netdev->name, j, p54u->fw_entry->size);
goto do_release;
}
data += P54U_FW_BLOCK;
i -= P54U_FW_BLOCK;
/* Magic */
p54u_dev_writel(netdev, ISL38XX_DIR_MEM_BASE_REG, 0xc0000f00);
p54u_dev_writel(netdev, 0x1020, 0);
p54u_dev_writel(netdev, 0x1020, 1);
p54u_dev_writel(netdev, 0x1024, len);
p54u_dev_writel(netdev, 0x1028, j | 0x00020000);
p54u_dev_writel(netdev, 0x0060, 0x20000000);
p54u_dev_writel(netdev, 0x0064, i > 0 ? 0x80 : 0x2e);
p54u_dev_writel(netdev, 0x0068, 4);
reg = p54u_dev_readl(netdev, 0x102c);
if(i > 0)
p54u_brg_writel(netdev, NET2280_EPA_STAT, NET2280_FIFO_FLUSH);
if(p54u->err) {
p54u_dbg("%s: Error updating registers: writen %i of %i.\n", netdev->name, j, p54u->fw_entry->size);
goto do_release;
}
j += P54U_FW_BLOCK;
}
reg = p54u_dev_readl(netdev, ISL38XX_CTRL_STAT_REG);
// reg |= ISL38XX_CTRL_STAT_RAMBOOT | ISL38XX_CTRL_STAT_CLKRUN;
reg |= ISL38XX_CTRL_STAT_RAMBOOT;
p54u_dev_writel(netdev, ISL38XX_CTRL_STAT_REG, reg);
p54u_dev_writel(netdev, ISL38XX_CTRL_STAT_REG, reg | ISL38XX_CTRL_STAT_RESET);
p54u_dev_writel(netdev, ISL38XX_CTRL_STAT_REG, reg);
if(p54u->err) {
p54u_dbg("%s: Error latching reset: %i\n", netdev->name, p54u->err);
}
p54u_info("%s: Load firmware done.\n", netdev->name);
return 0;
do_release:
do_err:
p54u_err("%s: Load error: %i\n", netdev->name, p54u->err);
err = p54u->err;
p54u->err = 0;
return err;
}
int p54u_setup_dev(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
struct p54u_mgmt_tx *tx1, *tx2;
u32 reg, rst = 0;
int i, j, k, pending, err;
p54u->err = usb_submit_urb(p54u->int_rx.urb[0], GFP_KERNEL);
if(p54u->err) {
p54u_dbg("%s: Error submit int 0: %i\n", netdev->name, p54u->err);
} else {
p54u_dbg("%s: Submit int 0 ok.\n", netdev->name);
}
p54u->err = usb_submit_urb(p54u->data_rx.urb[0], GFP_KERNEL);
if(p54u->err) {
p54u_dbg("%s: Error submit data: %i\n", netdev->name, p54u->err);
} else {
p54u_dbg("%s: Submit data ok.\n", netdev->name);
}
p54u->err = usb_submit_urb(p54u->mgmt_rx.urb[0], GFP_KERNEL);
if(p54u->err) {
p54u_dbg("%s: Error submit mgmt: %i\n", netdev->name, p54u->err);
} else {
p54u_dbg("%s: Submit mgmt ok.\n", netdev->name);
}
p54u_dev_writel(netdev, ISL38XX_INT_EN_REG, 0x80004004);
p54u_brg_writel(netdev, NET2280_IRQSTAT1, NET2280_PCI_INTA_INTERRUPT);
p54u_brg_writel(netdev, NET2280_USBIRQENB1, NET2280_PCI_INTA_INTERRUPT_ENABLE | NET2280_USB_INTERRUPT_ENABLE);
// p54u_dev_writel(netdev, ISL38XX_INT_EN_REG, 0xffffffff);
// p54u_dev_writel(netdev, ISL38XX_DEV_INT_REG, ISL38XX_DEV_INT_RESET | ISL38XX_DEV_INT_WAKEUP);
p54u_dev_writel(netdev, ISL38XX_DEV_INT_REG, ISL38XX_DEV_INT_RESET);
do {
pending = p54u_wait_int(netdev);
p54u_dev_writel(netdev, ISL38XX_INT_EN_REG, 0);
/* while((reg = p54u_dev_readl(netdev, ISL38XX_INT_IDENT_REG))) {
p54u_info("int: %08x\n", reg);
p54u_dev_writel(netdev, ISL38XX_INT_ACK_REG, reg);
}
*/ reg = p54u_dev_readl(netdev, ISL38XX_INT_IDENT_REG);
p54u_dev_writel(netdev, ISL38XX_INT_ACK_REG, reg);
p54u_brg_writel(netdev, NET2280_IRQSTAT1, NET2280_PCI_INTA_INTERRUPT);
p54u_dev_writel(netdev, ISL38XX_INT_EN_REG, 0x80004004);
// p54u_dev_writel(netdev, ISL38XX_INT_EN_REG, 0xffffffff);
// reg = p54u_brg_readl(netdev, NET2280_IRQSTAT1);
err = usb_submit_urb(p54u->int_rx.urb[0], GFP_KERNEL);
if(err) {
p54u_info("int resubmit failed %i\n", err);
break;
}
} while(pending);
/* Send the initial data to 0x02 pipe */
memset(p54u->mgmt_tx.buf[0], 0, p54u->mgmt_tx.size[0]);
memset(p54u->mgmt_tx.buf[1], 0, p54u->mgmt_tx.size[1]);
tx1 = p54u->mgmt_tx.buf[0];
tx2 = p54u->mgmt_tx.buf[1];
tx1->magic1 = 0x0002066c;
tx1->magic2 = 0x0002040c;
tx1->magic3 = 0;
tx1->pos = 0;
tx1->len = 0;
tx2->magic1 = 0x04008000;
tx2->magic2 = 0x813376b0;
tx2->magic3 = 0x0000000c;
tx2->pos = 0;
tx2->len = P54U_INIT_BLOCK;
for(i = 0; i < 1; i++) {
p54u_bulk_msg(netdev, P54U_PIPE_MGMT, tx1, 16);
p54u_dev_writel(netdev, ISL38XX_DEV_INT_REG, 0x80);
p54u_bulk_msg(netdev, P54U_PIPE_MGMT, tx2, P54U_INIT_BLOCK + 16);
// p54u_bulk_msg(netdev, P54U_PIPE_MGMT, tx2, 512);
tx2->pos += P54U_INIT_BLOCK;
p54u_mdelay(200);
}
return p54u->err;
}
int p54u_boot(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
int err;
p54u_info("%s: Boot the device.\n", netdev->name);
p54u_dbg("%s: Request firmware.\n", netdev->name);
err = request_firmware(&p54u->fw_entry, P54U_IMAGE_FILE, netdev->class_dev.dev);
if(err) {
p54u_err("%s: Request firmware failed: %i\n", netdev->name, err);
return err;
}
p54u_dbg("%s: Request firmware done: len = %i.\n", netdev->name, p54u->fw_entry->size);
p54u->time = get_jiffies_64();
err = p54u_reset_usb(netdev);
if(!err)
err = p54u_alloc_buffers(netdev);
if(!err)
err = p54u_reset_dev(netdev);
if(!err)
err = p54u_load_firmware(netdev);
if(!err)
err = p54u_setup_dev(netdev);
release_firmware(p54u->fw_entry);
memcpy(netdev->dev_addr, dummy_mac, ETH_ALEN);
p54u->running = 1;
if(err) {
p54u_err("%s: Boot the device failed: %i\n", netdev->name, err);
return err;
}
p54u_info("%s: Boot the device done.\n", netdev->name);
return 0;
}
int p54u_shutdown(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
u32 reg;
p54u_dbg("%s: Shutting down the device.\n", netdev->name);
p54u_free_buffers(netdev);
// reg = p54u_brg_readl(netdev, P54U_BRG_CTRL_REG);
// p54u_brg_writel(netdev, P54U_BRG_CTRL_REG, (reg | P54U_BRG_POWER_DOWN) & ~P54U_BRG_POWER_UP);
// p54u_brg_writel(netdev, P54U_BRG_CTRL_REG, 0x3e);
p54u->running = 0;
p54u_dbg("%s: Shutdown complete.\n", netdev->name);
return 0;
}
static int p54u_validate_device(struct usb_interface *interface, const struct usb_device_id *id)
{
/* See if the device offered us matches what we can accept */
return 0;
}
static int p54u_probe(struct usb_interface *interface, const struct usb_device_id *id)
{
struct usb_device *usbdev = interface_to_usbdev(interface);
struct net_device *netdev;
struct p54u *p54u;
p54u_dbg("Prism54 USB Device Probe (Device number:%d): 0x%4.4x:0x%4.4x:0x%4.4x", usbdev->devnum, (int) usbdev->descriptor.idVendor, (int) usbdev->descriptor.idProduct, (int) usbdev->descriptor.bcdDevice);
p54u_dbg("Device at %p", usbdev);
p54u_dbg("Descriptor length: %x type: %x", (int) usbdev->descriptor.bLength, (int) usbdev->descriptor.bDescriptorType);
if(p54u_validate_device(interface, id))
return -ENODEV;
netdev = alloc_etherdev(sizeof(*p54u));
if (!netdev) {
p54u_err("Failed to allocate netdevice.");
return -ENOMEM;
}
SET_MODULE_OWNER(netdev);
SET_NETDEV_DEV(netdev, &interface->dev);
usb_set_intfdata(interface, netdev);
p54u = netdev_priv(netdev);
p54u->interface = interface;
p54u->usbdev = usbdev;
p54u->netdev = netdev;
init_MUTEX (&p54u->disconnect_sem);
memcpy(netdev->dev_addr, dummy_mac, ETH_ALEN);
if(load_fw)
/* Dont error if it fails, give it chance on open. */
p54u_boot(netdev);
if(p54u_setup_net(netdev)) {
p54u_err("Failed to setup netdevice.");
goto do_cleanup;
}
if(register_netdev(netdev)) {
p54u_err("Failed to register netdevice.");
goto do_cleanup;
}
p54u_info("Prism54 USB device now attached to %s", netdev->name);
return 0;
do_cleanup:
p54u_free_buffers(netdev);
usb_set_intfdata(interface, NULL);
free_netdev(netdev);
return -EIO;
}
static void p54u_disconnect(struct usb_interface *interface)
{
struct net_device *netdev = usb_get_intfdata(interface);
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
p54u_info("Prism54 USB device %s disconnecing\n", netdev->name);
p54u_dbg("sem down\n");
down(&p54u->disconnect_sem);
p54u_dbg("sem down done\n");
p54u->running = 0;
p54u_dbg("Running = 0.\n");
usb_set_intfdata(interface, NULL);
p54u_dbg("Cleared interface data.\n");
unregister_netdev(netdev);
p54u_dbg("Unregistered netdevice.\n");
p54u_free_buffers(netdev);
p54u_dbg("Freed buffers.\n");
free_netdev(netdev);
p54u_dbg("Freed netdevice.\n");
p54u_info("Disconnect complete.\n");
p54u_dbg("sem up\n");
up(&p54u->disconnect_sem);
p54u_dbg("sem up done\n");
}
static struct usb_driver p54u_driver = {
.owner = THIS_MODULE,
.name = driver_name,
.probe = p54u_probe,
.disconnect = p54u_disconnect,
.id_table = p54u_table,
};
static int __init p54u_init(void)
{
int result;
/* register this driver with the USB subsystem */
result = usb_register(&p54u_driver);
if (result) {
p54u_err("usb_register failed. Error number %d", result);
return result;
}
return 0;
}
static void __exit p54u_exit(void)
{
/* deregister this driver with the USB subsystem */
usb_deregister(&p54u_driver);
}
module_init(p54u_init);
module_exit(p54u_exit);
--Multipart=_Sun__4_Apr_2004_16_03_46_+0200_t4U0QFKPIx=mIm5z
Content-Type: text/x-csrc;
name="usb_netdev.c"
Content-Disposition: attachment;
filename="usb_netdev.c"
Content-Transfer-Encoding: 7bit
/*
* Prism54 USB driver
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/smp_lock.h>
#include <linux/completion.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <asm/uaccess.h>
#include <linux/usb.h>
#include "prism54_usb.h"
#include "isl_38xx.h"
const char dummy_mac[ETH_ALEN] = {0x00, 0x3d, 0xb4, 0x00, 0x00, 0x00};
static int p54u_open(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
p54u_info("sem down\n");
down (&p54u->disconnect_sem);
p54u_info("sem down done\n");
if(!p54u->running && p54u_boot(netdev)) {
p54u_err("Failed to boot device.\n");
goto do_err;
}
netif_start_queue(netdev);
p54u_info("sem up\n");
up(&p54u->disconnect_sem);
p54u_info("sem up done\n");
return 0;
do_err:
p54u_err("Failed to open device.\n");
p54u_info("sem up\n");
up(&p54u->disconnect_sem);
p54u_info("sem up done\n");
return -EIO;
}
static int p54u_close(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
netif_stop_queue(netdev);
if(!load_fw && p54u->running && p54u_shutdown(netdev))
return -EIO;
return 0;
}
static void p54u_tx_timeout(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
return;
}
static int p54u_transmit(struct sk_buff *skb, struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
return 0;
}
int p54u_setup_net(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
/* initialize the function pointers */
netdev->open = &p54u_open;
netdev->stop = &p54u_close;
// netdev->get_stats = &p54u_statistics;
// netdev->get_wireless_stats = &p54u_wireless_stats;
// netdev->do_ioctl = &p54u_ioctl;
// netdev->wireless_handlers = (struct iw_handler_def *) &p54u_handler_def;
netdev->hard_start_xmit = &p54u_transmit;
netdev->addr_len = ETH_ALEN;
// netdev->set_mac_address = &prism54_set_mac_address;
netdev->watchdog_timeo = P54U_TX_TIMEOUT;
netdev->tx_timeout = &p54u_tx_timeout;
return 0;
}
--Multipart=_Sun__4_Apr_2004_16_03_46_+0200_t4U0QFKPIx=mIm5z
Content-Type: text/x-csrc;
name="usb_transport.c"
Content-Disposition: attachment;
filename="usb_transport.c"
Content-Transfer-Encoding: 7bit
/*
* Prism54 USB driver
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/smp_lock.h>
#include <linux/completion.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/usb.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <asm/uaccess.h>
#include "prism54_usb.h"
#include "isl_38xx.h"
void p54u_mdelay(int ms)
{
int t = (ms * HZ + 500) / 1000;
if(!t && ms)
t = 1;
set_current_state(TASK_UNINTERRUPTIBLE);
while(t) {
//printk("t: %i\n", t);
t = schedule_timeout(t);
}
return;
}
void p54u_data_debug(struct net_device *netdev, unsigned int ep, void *_data, int len)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
unsigned char *data = _data;
int k, l, in;
in = ep & USB_DIR_IN;
if(debug > 1) {
for(k = 0; k < len; k+= 16) {
if(k == 0) {
printk(KERN_CRIT "[%s >%-6lld<%-6lld+%-6lld] %02x %s 00000000:", in?"IN ":"OUT", 0LL, 0LL, 0LL, ep, in?"<-":"->");
} else {
printk(KERN_CRIT " -> %08x:", k);
}
for (l = 0; (l < 16) && (k + l < len); ++l) {
printk(" %02x", ((unsigned char *)data)[k + l]);
}
printk("\n");
}
}
}
int p54u_bulk_msg(struct net_device *netdev, unsigned int ep, void *_data, int len)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
unsigned char *data = _data;
size_t alen;
int pipe, err, k, l;
p54u_data_debug(netdev, ep, data, len);
pipe = usb_sndbulkpipe(usbdev, ep);
err = usb_bulk_msg(usbdev, pipe, data, len, &alen, 2 * HZ);
if(err)
p54u_info("bulk submit failed: %i\n", err);
return err;
}
u32 p54u_reg_rw(struct net_device *netdev, int write, int ep, int port, u32 addr, u32 val)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
struct p54u_reg reg;
unsigned int pipe;
size_t len;
int err, i, epd;
u64 t, t1, t2;
reg.port = cpu_to_le16(port);
reg.addr = cpu_to_le32(addr);
reg.val = ((port & P54U_PORT_U32) == P54U_PORT_U32) ? cpu_to_le32(val) : cpu_to_le16(val);
len = write ? P54U_REG_WSIZE : P54U_REG_RSIZE;
pipe = usb_sndbulkpipe(usbdev, ep & USB_ENDPOINT_NUMBER_MASK);
t1 = p54u_time();
err = usb_bulk_msg(usbdev, pipe, ®, len, &len, HZ);
t2 = p54u_time();
t = t2 - t1;
p54u_data_debug(netdev, ep, ®, len);
if(err) {
p54u_err("%s %02x %04x %08x %08x: failed: %i", write ? "Write": "Read", ep, port, addr, val, err);
p54u->err = err;
return 0;
}
if(write) {
// udelay(ISL38XX_WRITEIO_DELAY);
return 0;
}
pipe = usb_rcvbulkpipe(usbdev, ep & USB_ENDPOINT_NUMBER_MASK);
len = sizeof(reg.val);
t1 = p54u_time();
err = usb_bulk_msg(usbdev, pipe, ®.val, len, &len, HZ);
t2 = p54u_time();
t = t2 - t1;
if(err) {
p54u_err("Register read %02x %04x %08x %08x: failed: %i", ep, port, addr, val, err);
p54u->err = err;
return 0;
}
p54u_data_debug(netdev, ep | USB_DIR_IN, ®.val, len);
return ((port & P54U_PORT_U32) == P54U_PORT_U32) ? le32_to_cpu(reg.val) : le16_to_cpu(reg.val);
}
int p54u_wait_int(struct net_device *netdev)
{
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
int err, pending;
wait_for_completion(&p54u->int_rx.comp);
printk("readi: %08x\n", p54u->pending);
pending = p54u->pending;
return pending;
}
void p54u_int_rx_cb(struct urb *urb, struct pt_regs *p)
{
struct net_device *netdev = urb->context;
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
int err, pending;
u32 reg;
u64 t;
t = p54u_time();
pending = *(int *)urb->transfer_buffer;
p54u_data_debug(netdev, 0x8f, urb->transfer_buffer, urb->actual_length);
p54u->pending = pending;
complete(&p54u->int_rx.comp);
return;
}
void p54u_data_rx_cb(struct urb *urb, struct pt_regs *p)
{
struct net_device *netdev = urb->context;
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
int err;
p54u_data_debug(netdev, 0x81, urb->transfer_buffer, urb->actual_length);
return;
}
void p54u_mgmt_rx_cb(struct urb *urb, struct pt_regs *p)
{
struct net_device *netdev = urb->context;
struct p54u *p54u = netdev_priv(netdev);
struct usb_device *usbdev = p54u->usbdev;
unsigned char *data;
size_t len;
int err, k, l;
u64 t;
p54u_data_debug(netdev, 0x82, urb->transfer_buffer, urb->actual_length);
return;
}
--Multipart=_Sun__4_Apr_2004_16_03_46_+0200_t4U0QFKPIx=mIm5z--